DocumentCode
2827745
Title
A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations
Author
Takahashi, Hiroshi ; Boateng, Kwame Osei ; Takamatsu, Yuzo
Author_Institution
Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
fYear
1999
fDate
1999
Firstpage
64
Lastpage
69
Abstract
In this paper, we propose a new method that uses single and multiple fault simulations to diagnose multiple stuck-at faults in combinational circuits. On the assumption that all suspected faults are equally likely in the faulty circuit, multiple fault simulations are performed. Depending on whether or not a multiple fault simulation results in primary output values that agree with the observed values, faults are added to or removed from a set of suspected faults. Faults which are to be added to or removed from the set of suspected faults are determined using single fault simulation. Diagnosis is effected by repeated additions and removals of faults. The effectiveness of the method of diagnosis has been evaluated by experiments conducted on benchmark circuits. The proposed method achieves a small number of suspected faults by simple processing. Thus, the method will be useful as a preprocessing stage of diagnosis using the electron-beam tester
Keywords
VLSI; combinational circuits; electron beam testing; fault diagnosis; fault simulation; logic testing; benchmark circuits; combinational circuits; electron-beam tester; multiple fault simulations; multiple stuck-at faults; preprocessing stage; primary output values; single fault simulations; suspected faults; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Fault diagnosis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
0-7695-0146-X
Type
conf
DOI
10.1109/VTEST.1999.766648
Filename
766648
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