Title :
A Novel Reconfigurable Architecture for Temporal and Spatial Application Mapping
Author :
Danilin, Alexander ; Sawitzki, Sergei
Author_Institution :
NXP Semicond. Res., Eindhoven
Abstract :
This paper introduces a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Based on our previous work concerning DSP applications mapping onto ASTRA reconfigurable architecture, this paper describes the microarchitecture in more detail and introduces some significant improvements. The silicon area of the logic tile is reduced by 40%. The area figures of the benchmarks are only factor 10-25 worse than the ASIC implementation - a very competitive ratio for a reconfigurable architecture.
Keywords :
digital signal processing chips; field programmable gate arrays; logic design; reconfigurable architectures; ASTRA reconfigurable architecture; DSP application mapping; FPGA; field programmable gate array; logic-cell level; microarchitecture; temporal-spatial application mapping; Clustering algorithms; Computer architecture; Field programmable gate arrays; Hardware; Microarchitecture; Partitioning algorithms; Reconfigurable architectures; Reconfigurable logic; Silicon; Tiles;
Conference_Titel :
Programmable Logic, 2007. SPL '07. 2007 3rd Southern Conference on
Conference_Location :
Mar del Plata
Print_ISBN :
1-4244-0606-4
DOI :
10.1109/SPL.2007.371726