Title :
Test generation for ground bounce in internal logic circuitry
Author :
Chang, Yi-Shing ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce
Keywords :
VLSI; automatic test pattern generation; combinational circuits; delays; integrated circuit testing; logic testing; circuit model; combinational logic; delay testing; design validation; ground bounce; internal logic circuitry; test generation; test patterns; Circuit noise; Circuit simulation; Circuit testing; Crosstalk; Design engineering; Inductance; Logic circuits; Logic testing; Power system modeling; Threshold voltage;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766652
