DocumentCode :
2827944
Title :
Adaptive techniques for improving delay fault diagnosis
Author :
Ghosh-Dastidar, Jayabrata ; Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear :
1999
fDate :
1999
Firstpage :
168
Lastpage :
172
Abstract :
This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failure analysis. Given a set of two-pattern tests that resulted in faulty output responses, a procedure for deriving additional two-pattern tests that will improve the diagnostic resolution of delay faults is described. Two new techniques based on adjacency testing and delay-size bounding are presented. These techniques can be used to greatly reduce the number of suspect lines and thereby provide a more precise diagnosis that is valid for either single or multiple delay faults. Experimental results are shown indicating that the number of suspects can be reduced dramatically for both single and multiple delay faults
Keywords :
VLSI; delays; digital integrated circuits; failure analysis; fault diagnosis; integrated circuit testing; logic testing; adaptive techniques; adjacency testing; delay fault diagnosis; delay-size bounding; diagnostic resolution; direct probing; failure analysis; faulty output responses; multiple delay faults; search space reduction; single delay faults; two-pattern tests; Automatic test pattern generation; Chemicals; Circuit faults; Clocks; Delay; Failure analysis; Fault diagnosis; Frequency; Testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
ISSN :
1093-0167
Print_ISBN :
0-7695-0146-X
Type :
conf
DOI :
10.1109/VTEST.1999.766661
Filename :
766661
Link To Document :
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