An Efficient Scalable Parallel Hardware Architecture for Multilayer Spiking Neural Networks

Artificial neural networks (ANNs) are processing models widely explored due to their computational capabilities for solving problems. Recently, spiking neural networks (SNNs) are being studied as more biological plausible models that resemble closer to biological neurons than classical ANNs. In spite of SNNs offer richer dynamics, their full utilization in practical systems is still limited due to high computational demand on microprocessors-based software implementations. In order to overcome this drawback, an efficient scalable parallel hardware architecture for SNNs is proposed to map efficiently area demanding and dense interconnection requirements of neural processing. The SNNs models have the advantage of reducing the bandwidth needed for interchanging information among neurons, making them more suitable for hardware implementation, due to the communication scheme based on digital spikes. The hardware implementation is divided into two main phases: recall and learning. Timing, hardware resources and performance comparison are mainly shown for the recall phase in this paper.