DocumentCode :
2828236
Title :
A new bare die test methodology
Author :
Yang, Zao ; Cheng, K.-T. ; Tai, K.L.
Author_Institution :
Silicon Graphics Inc., Mountain View, CA, USA
fYear :
1999
fDate :
1999
Firstpage :
290
Lastpage :
295
Abstract :
While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that makes the technology economically unattractive is the problems and the high cost associated with testing and diagnosing each individual un-packaged IC in the system and the MCM module itself. The low MCM system yield prevents the technology from being used other than in high cost and high performance applications. In this paper, we propose a new methodology using ideas of tester-on-a-chip and a pressure contact technology to test bare dies. This methodology can reduce the IC testing cost and overall cost of the MCM module. It can also be considered as an alternative to high speed wafer probe. We designed an experiment for SRAM dies to examine the feasibility of this new method
Keywords :
SRAM chips; VLSI; integrated circuit economics; integrated circuit testing; multichip modules; production testing; IC testing cost; SRAM dies; bare die test methodology; overall cost; pressure contact technology; tester-on-a-chip; Binary search trees; Capacitance; Electronic equipment testing; Frequency; Integrated circuit noise; Needles; Noise reduction; Probes; Sockets; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
ISSN :
1093-0167
Print_ISBN :
0-7695-0146-X
Type :
conf
DOI :
10.1109/VTEST.1999.766678
Filename :
766678
Link To Document :
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