Title :
A systematic DFT procedure for library cells
Author :
Xu, Jingjing ; Kundu, Rahul ; Ferguson, F. Joel
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
We present an automated procedure for improving the testability of a product by improving the testability of cells in the cell library. This method was applied to a scan flip-flop from Cyrix´s standard cell library. Based on this analysis, some design and layout changes were suggested, which brought down the probability of difficult-to-detect faults by 70%, without compromising the performance or increasing the area of the circuit
Keywords :
cellular arrays; circuit layout CAD; design for testability; flip-flops; logic CAD; sequential circuits; software libraries; Cyrix; automated procedure; circuit area; difficult-to-detect faults; layout changes; library cells; scan flip-flop; standard cell library; systematic DFT procedure; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Data mining; Design for testability; Fabrication; Fault detection; Libraries; Sequential analysis;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766704
