Scheduling and allocation of single-chip multiprocessors for multimedia

Software synthesis is an increasingly important problem in the design of digital signal processing systems, since multimedia systems in particular are increasingly implemented using a combination of programmable and hardwired processing elements. This paper describes new algorithms for system-level software synthesis, namely the scheduling and allocation of a set of tasks executing on a heterogeneous multiprocessor. The algorithm is hierarchical: it takes advantage of the hierarchical structure of the system´s task graph to hierarchically allocate and schedule processes on the multiprocessor to meet the hard real-time constraints on the tasks. Our algorithm takes into account both the on-chip and off-chip data communications and the behaviors of data cache memories. It can significantly improve task schedulability by carefully scheduling processes and data transfers to minimize data cache misses and off-chip data accesses