Exploration of vertical MOSFET and tunnel FET device architecture for Sub 10nm node applications

Author

Liu, H. ; Mohata, D.K. ; Nidhi, A. ; Saripalli, V. ; Narayanan, V. ; Datta, S.

Author_Institution

Pennsylvania State Univ., University Park, PA, USA

fYear

2012

fDate

18-20 June 2012

Firstpage

233

Lastpage

234

Abstract

A vertical device architecture having -40% density improvement over planar for sub-10nm technology node has been evaluated for Si NMOS and III-V HTFET with L_g=16nm. For LOP applications including the effect of parasitic elements, the HTFET presents superior energy efficiency and desired low-power analog performance for V_DD<;0.6V, while MOSFET is superior for V_DD>;0.6V. To further improve MOSFET performance, I_ON needs to be improved with higher injection velocity materials (e.g. III-V). For delay reduction, the parasitic capacitances (C_ov and C_g,fringe) and contact resistance need to be further engineered for both MOSFETs and TFETs.

Keywords

III-V semiconductors; MOSFET; contact resistance; low-power electronics; tunnel transistors; III-V HTFET; LOP applications; NMOS; contact resistance; delay reduction; density improvement over planar; energy efficiency; injection velocity materials; low-power analog performance; parasitic capacitances; parasitic elements effect; size 10 nm; sub 10nm node applications; sub-0nm technology node; tunnel FET device architecture; vertical MOSFET; vertical device architecture; CMOS integrated circuits; CMOS technology; FinFETs; Inverters; Logic gates;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference (DRC), 2012 70th Annual

Conference_Location

University Park, TX

ISSN

1548-3770

Print_ISBN

978-1-4673-1163-2

Type

conf

DOI

10.1109/DRC.2012.6256990

Filename

6256990