An Evaluation of Two-Stage Systematic Sampling in Micro-Architecture Simulation

Software simulation is the most important method for computer architects to evaluate the function and performance of their new designs. Due to the prohibitively long simulation time when running the full dynamic instruction streams of benchmarks on simulators in detailed simulation mode, many use sampling simulation to accelerate the simulation speed without sacrificing the accuracy greatly. However, the simulation speed of most existing simulators still can not satisfy the computer architects. This paper presents the two-stage systematic sampling (TSSS) approach to accelerate the micro-architecture simulation. As other simulation sampling methods, only a subset of benchmark instructions are simulated and measured in detail. But selecting the instructions through two-stage systematic sampling approach has advantages in theory and practice. Tests of 7 benchmarks from SPEC CPU2000 show that this approach can achieve only 0.06% IPC error while the simulation time is only 1/23 of the time needed by sim-outorder. In the same condition, the IPC error of SMARTS which is the best existing simulator is 1.14% and the simulation time of SMARTS is 1/21 of the time needed by sim-outorder. TSSS approach can reduce the simulation time from SMARTS´ 1/19 to 1/26 of the time needed by sim-outorder while the IPC error is only lost 0.65%.