Hierarchical decomposition system and its availability for network solution

For efficient circuit simulation, several network tearing techniques have been studied. The authors describe a hierarchical decomposition system, HIDE, and verify its availability for the network solution by the direct method. This system has a graphic circuit editor, GRACE, a translator, LINKER, into the hierarchical structural description language HAL, and the subsystem HiDe, which performs automatic partition of the circuit into gate level subcircuits hierarchically, utilizing the HAL netlist. The authors discuss the hierarchical tearing algorithm for large scale circuits. The authors apply this system to transistor-transistor-logic (TTL) and MOS circuits and verify its availability for the matrix solution