Simulation study of nanowire tunnel FETs

Tunnel FETs (TFETs) are candidates for low-power logic switches with sub-thermal slope which could enable a strongly reduced supply voltage. To improve the ON-current compared to Si TFETs, III-V/Si hetero junctions have been proposed [1]. Using nanowires has additional advantages: (i) the possibility of many different material combinations [2], (ii) efficient strain relaxation in the case of small diameters [2], (iii) a good electrostatic control due to the surrounding gate. Tomioka et al. [3,4,5] and Björk et al. [6] have advanced the integration of InAs nanowires on Si with nanometer-scale hetero epitaxy. The present simulation study refers to their experimental data.