Title :
Gate-first implant-free InGaAs n-MOSFETs with sub-nm EOT and CMOS-compatible process suitable for VLSI
Author :
Czornomaz, L. ; El Kazzi, M. ; Caimi, D. ; Rossel, C. ; Uccelli, E. ; Sousa, M. ; Marchiori, C. ; Richter, M. ; Siegwart, H. ; Fompeyrine, J.
Author_Institution :
IBM Zurich Res. Lab., Rüschlikon, Switzerland
Abstract :
We have demonstrated the first InGaAs MOSFETs with sub-nm EOT featuring a gate-first implant-free process compatible with VLSI. At LG = 65 nm, these devices are among the best reported ones in terms of electrostatic integrity but they suffer from a large access resistance related to a large gate-to-source/drain spacing. Future work will focus on scaling this spacing in the 5 nm range in order to achieve the desired on-performance.
Keywords :
CMOS integrated circuits; III-V semiconductors; MOSFET; VLSI; gallium arsenide; indium compounds; CMOS-compatible process; EOT; InGaAs; VLSI; access resistance; electrostatic integrity; gate-first implant-free n-MOSFET process; gate-to-source-drain spacing; size 65 nm; Electrostatics; Logic gates; MOSFET circuits; Silicon; Thermal stability; Very large scale integration; Voltage measurement;
Conference_Titel :
Device Research Conference (DRC), 2012 70th Annual
Conference_Location :
University Park, TX
Print_ISBN :
978-1-4673-1163-2
DOI :
10.1109/DRC.2012.6257044
