An alternative combining architecture for large-scale shared-memory multiprocessors

Investigates an alternative combining architecture for removing degradation of the multiprocessor interconnection network due to hot-spot contention, which results in drastically inferior performance. Based on a combining tree, the proposed combining architecture has much lower hardware complexity than the prior combining network and yet can effectively eliminate hot-spot contention. Simulation results confirm that the mean latency of hot-spot requests through the alternative combining architecture is low, provided that the concurrent hot-spot number is reasonably small (say, no more than 8). A fault-tolerant technique for the combining architecture is also addressed to significantly enhance its reliability at a little extra cost