Title :
Verification and diagnosis of SoC HDL-code
Author :
Hahanov, Vladimir ; Park, Dong Won ; Guz, Olesya ; Priymak, Aleksey
Author_Institution :
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
Abstract :
Xor-metrix for object relations in a vector logic space and a structural testing model are proposed. Assertion-based models and methods for the verification and diagnosis of HDL-code functional failures, which make possible to reduce considerably time-to-market of software and hardware, are developed. An architectural model of multimatrix reduced logical instruction set processor for embedded diagnosing is offered.
Keywords :
fault tolerant computing; hardware description languages; instruction sets; system-on-chip; HDL-code functional failure diagnosis; SoC HDL-code verification; XOR-metrix; architectural model; assertion-based models; embedded diagnosis; multimatrix reduced logical instruction set processor; structural testing model; time-to-market; vector logic space; Analytical models; Engines; Mathematical model; Monitoring; Software; Testing; Vectors;
Conference_Titel :
Design & Test Symposium (EWDTS), 2011 9th East-West
Conference_Location :
Sevastopol
Print_ISBN :
978-1-4577-1957-8
DOI :
10.1109/EWDTS.2011.6116418
