Title :
State assignment for asynchronous state machines
Author :
May, Trevor C. ; Girczyc, Emil F.
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
A state assignment method is described for asynchronous circuits based on simulated annealing that produces race-free multiple transition time assignments. Simulated annealing is used to obtain a good initial assignment. An algorithmic cleanup procedure is used to guarantee that each state transition is race free. The user is allowed to specify timing constraints on the resulting logic, which influences state assignment to assign adjacent states where fast transitions are required. The system has been implemented in C++, and has been tested on a variety of circuits with up to 100 states
Keywords :
asynchronous sequential logic; hazards and race conditions; logic CAD; simulated annealing; state assignment; C++ implementation; algorithmic cleanup procedure; asynchronous state machines; multiple transition time assignments; race free transition; simulated annealing; state assignment method; timing constraints; Circuit simulation; Circuit testing; Clocks; Hazards; Logic; Simulated annealing; Space heating; Synchronization; System testing; Timing;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140923
