Title :
Power supply ripple reduction techniques for switched-capacitor circuits
Author :
Lee, Bang W. ; Bae, Yi S. ; Baek, Sang Y.
Author_Institution :
Samsung Electronics Co., KyungGi-Do, South Korea
Abstract :
In mixed-mode MOS VLSI circuits switching noises generated in digital circuits are inevitably coupled into analog circuits through commonly shared power lines and substrate layer. Three design techniques to reduce the power ripple coupling, which include optimizing individual SC integrators, minimizing input transistor area and applying a stable bias potential, are described. Experimental results using the optimizing technique show more than 8-dB ripple reduction in a switched-capacitor circuit
Keywords :
MOS integrated circuits; VLSI; switched capacitor networks; MOS VLSI circuits; SC integrators; analog circuits; analogue-digital ICs; digital circuits; input transistor area; mixed-mode ICs; optimizing technique; power ripple coupling; shared power lines; stable bias potential; substrate layer; supply ripple reduction; switched-capacitor circuits; switching noises; Analog circuits; Circuit noise; Coupling circuits; Design optimization; Digital circuits; Noise generators; Power generation; Power supplies; Switching circuits; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176680
