DocumentCode
2832253
Title
Design of A 1.2-v 6-GHz 1.19-mW Divide-by-32/33 Prescaler
Author
Xu Tailong ; Meng Jian
Author_Institution
Sch. of Electron. Sci. & Technol., Anhui Univ., Hefei, China
fYear
2009
fDate
19-20 Dec. 2009
Firstpage
1
Lastpage
3
Abstract
Based on divide-by-4/5 divider, a divide-by-32/33 dual modulus prescaler is designed with characteristics of high operating frequency, low supply voltage and low power dissipation. The circuit is simulated by the simulator, Eldo under the TSMC 90 nm low power CMOS process. The simulated results show that the highest operating frequency is up to 6 GHz, and drains only 0.99 mA from a 1.2 V supply voltage.
Keywords
CMOS logic circuits; field effect MMIC; flip-flops; frequency dividers; integrated circuit design; logic gates; low-power electronics; prescalers; Eldo; OR gates; SCL D flip-flops; TSMC low power CMOS process; current 0.99 mA; divide-by-32/33 dual modulus prescaler; divide-by-4/5 divider; frequency 6 GHz; high operating frequency; low power dissipation; low supply voltage; voltage 1.2 V; CMOS process; Circuit simulation; Counting circuits; Frequency conversion; Frequency synthesizers; Logic; Low voltage; Power dissipation; Radio frequency; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Engineering and Computer Science, 2009. ICIECS 2009. International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-4994-1
Type
conf
DOI
10.1109/ICIECS.2009.5364198
Filename
5364198
Link To Document