Simultaneous pin assignment and global wiring for custom VLSI design

The problem of determining the interconnections among component modules for top-down VLSI layout design is discussed. Two main steps, pin assignment and global routing, are attacked simultaneously. They are integrated and formulated into one special Steiner minimal tree problem. An algorithm is then presented to solve it. Also, the local resident effect of many interconnection nets on a layout is considered. A strategy based upon this effect is proposed to speed up this algorithm. The strategy finds a smaller area called a critical routing area for a net to be passed through. Experimental results show that the performance is increased without reducing the routing quality