BiCMOS defect-modelling and fault analysis

Author

Stewart, Bradley E. ; Al-Khalili, Dhamin ; Rozon, Come

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2152

Abstract

Common defects are modeled for BiCMOS logic gates. Only 54% of the defect set simulated in the BiCMOS test circuits manifested themselves in terms of a failure in the logical behavior of the gate. This would suggest that test vector sets designed on the premise of testing for logical failures would be less appropriate for BiCMOS than for CMOS gates where 69% of the defect set caused logical failures. However, 95% of the defects simulated in the BiCMOS test circuits caused failures that could be characterized as either a failure in the logical behavior of the gate or as a delay fault. These results indicate that, by applying logical-fault testing in combination with delay-fault testing, fault coverage should be increased to more acceptable levels

Keywords

BIMOS integrated circuits; failure analysis; integrated logic circuits; logic gates; logic testing; defect-modelling; delay fault; fault analysis; logic gates; logical failure testing; logical-fault testing; test circuits; test vector sets; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Logic gates; Logic testing; Resistors; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176712

Filename

176712