Circuit optimization as a tool for the design of 1.0-2.0 GHz CMOS topologies

The authors demonstrate design techniques for high-speed CMOS circuits. Future, integrated telecommunication systems operating within the signal frequency range of 1.0-2.0 GHz will require state-of-the-art semiconductor technologies, system solutions and design tools for the optimization of the most important specifications, like speed-power, temperature stability, noise, and linearities. The authors describe the technological requirements, circuit solutions and the optimization techniques that are suitable for integrating analog-digital RF functions with a scaled CMOS technology