Classification for 2D-DCTs and a new architecture with distributed arithmetic

Author

Wolter, S. ; Birreck, D. ; Laur, R.

Author_Institution

Inst. fur Mikroelektronik, Bremen Univ., Germany

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2204

Abstract

Some highlights in the development of special-purpose circuits for the two-dimensional discrete cosine transform (2D-DCT) are given. In order to give a survey on the efforts made in processor design around the world, a classification of already realized and suggested VLSI architectures is proposed. The authors also present a novel architecture with a moderately fast algorithm. It exploits the computation of an N-point DCT with N/2 DCTs in a row-column decomposition. The computation of the inner products of the N/2 DCTs is realized with distributed arithmetic. A circuit is proposed, realizing both the forward and inverse transform on the same chip

Keywords

VLSI; application specific integrated circuits; bandwidth compression; computerised picture processing; data compression; digital arithmetic; digital signal processing chips; transforms; 2D-DCT; VLSI architectures; distributed arithmetic; fast algorithm; forward transform; inverse transform; row-column decomposition; special-purpose circuits; two-dimensional discrete cosine transform; Arithmetic; Circuits; Computer architecture; Discrete cosine transforms; Discrete transforms; HDTV; Hardware; Kernel; Matrix decomposition; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176736

Filename

176736