Application of VLSI technology to the Z-J stack algorithm

The Z-J algorithm given by A.J. Viterbi (1967) and K. Zigangirov (1966) is a bit-error correcting algorithm for long constraint length convolutional codes. The feasibility of implementing the algorithm in a single VLSI chip to obtain bit error correction for systems with input data rates approaching on-chip clock rates, which currently range up to hundreds of megabits/s, is described. Simulations of the algorithm under VLSI constraints demonstrate potential error correction performance superior to available maximum likelihood decoders, which operate at shorter constraint length, at noise levels below decoding limits for sequential decoders. Stack dimensions required to achieve the result are on the order of 250×100 bits