Signed multiple-valued PLAs and the design of fast multiple-valued arithmetic operation units for systolic MV-DTW processor

Author

Feng Zhao Zhi ; Shan, Hua ; Huang Ze Liu ; Chen Dao Wen

Author_Institution

Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2216

Abstract

Three new types of multiple-valued programmable logic arrays (MVPLAs) are proposed. Type 1 MVPLA consists of signed literal generators, a MIN array, and MAX arrays. Type 2 MVPLA consists of signed literal generators, an AND array and an OR array, and signed output encoders. Type 3 MVPLA is a two-level PLA which combines the type 2 MVPLA with a two-valued PLA with signed two-bit decoders. The principle of fast multiple-valued arithmetic operation units (addition, absolute value subtraction, and minimization) are presented, and their design is also discussed

Keywords

digital arithmetic; logic arrays; many-valued logics; speech recognition; systolic arrays; AND array; MAX arrays; MIN array; OR array; absolute value subtraction; dynamic time warp processor; minimization; multiple-valued arithmetic operation units; multiple-valued programmable logic arrays; signed literal generators; signed multiple valued PLAs; signed output encoders; two-level PLA; Arithmetic; Automatic speech recognition; Design automation; Information science; Logic arrays; Logic functions; Minimization; Pattern recognition; Programmable logic arrays; Speech recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176741

Filename

176741