An advanced programmable 2D-convolution chip for, real time image processing

An advanced defect-tolerant systolic array implementation of the 2-D convolution algorithm for real-time image processing applications is presented. The chip differs from available convolution chips in the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines, and implemented special processing of frame borders. Defect tolerance, e.g., reconfiguration techniques, are implemented in order to enhance yield and reliability, especially for future large area implementations