Title :
A semicustom clock/timer chip
Author :
Ling, Edward Chin Hsi ; Soon, Yip Chee
Author_Institution :
Nanyang Technol. Inst., Singapore
Abstract :
The authors describe the design and simulation of a gate-array based 7-day programmable clock chip. Modifications to the design to improve testability and suitability for simulation are discussed. The authors detail the various steps in the simulation and design verification. The strategy for generating simulation vectors is also discussed. Due to the high pin count, a 64-lead package was chosen for the chip. The circuitry was implemented in a 5-μm CMOS double-metal gate array design for a prototype. Schematic, layout data, and simulation files were sent to the foundry to fabricate the chips
Keywords :
CMOS integrated circuits; application specific integrated circuits; clocks; logic arrays; timing circuits; 5 micron; 64-lead package; ASIC; CMOS double-metal; design verification; gate-array; programmable clock chip; semicustom; simulation vectors; testability; timer chip; Clocks; Counting circuits; Flip-flops; Hardware; Liquid crystal displays; Oscillators; Pins; Pulse generation; Testing; Timing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176781
