Title :
Identification of gates for covering all critical paths
Author :
Khan, M. Moiz ; Tragoudas, Spyros ; Abadir, Magdy ; Liu, Brandon
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A zero-suppressed binary decision diagram (ZBDD) based method is presented to identify a small set of gates so that every critical path contains at least one of the selected gates. All paths above a threshold Dth are stored in a ZBDD. Static implications are used to eliminate unsensitizable paths. A min-cut method on the ZBDD is then used to identify a small set of gates in the circuit for buffer insertion or resizing to optimize delay of the whole circuit. It is observed that the methodology identifies a very small set of gates and its effectiveness demonstrated experimentally on ISCAS´85 and ITC99 benchmarks.
Keywords :
binary decision diagrams; circuit optimisation; delay circuits; logic gates; buffer insertion; buffer resizing; critical paths; min-cut method; unsensitizable paths; zero-suppressed binary decision diagram; Boolean functions; Circuit faults; Circuit testing; Coupling circuits; Data structures; Degradation; Delay effects; Optimization methods; Performance analysis; Timing;
Conference_Titel :
Microprocessor Test and Verification (MTV'04), Fifth International Workshop on
Print_ISBN :
0-7695-2320-X
DOI :
10.1109/MTV.2004.15
