Title :
SMART (strategic memory allocation for real-time) cache design using the MIPS R3000
Author :
Kirk, David B. ; Strosnider, Jay K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
SMART, a technique for providing predictable cache performance for real-time systems with priority-based preemptive scheduling, is presented. The technique is implemented in a R3000 cache design. The value density acceleration (VDA) cache allocation algorithm is also introduced, and shown to be suitable for run-time cache allocation
Keywords :
buffer storage; real-time systems; scheduling; storage allocation; MIPS R3000; SMART; cache allocation algorithm; cache design; predictable cache performance; priority-based preemptive scheduling; real-time systems; strategic memory allocation for real-time; value density acceleration; Cache memory; Dynamic scheduling; Kirk field collapse effect; Power engineering computing; Processor scheduling; Real time systems; Scheduling algorithm; Solid state circuits; Space technology; Timing;
Conference_Titel :
Real-Time Systems Symposium, 1990. Proceedings., 11th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
0-8186-2112-5
DOI :
10.1109/REAL.1990.128764
