A probabilistic timing analysis for synthesis in microprocessor interface design

Systems are constructed by connecting simpler modules. Interfaces are used to achieve inter-module connectivity. This work addresses the problem of verifying the correctness of the interface timed behavior in advance of its implementation. A technique called timing analysis for synthesis (TAFS) models the interface path delays as random variables and finds the tightest bounds on those variables which satisfy the timing constraints given in the specifications. Such a model allows the designer to perform a reliability analysis in addition to finding bounds on the timing parameters of the interface design