Title :
The mapping of logic designs into a very large scale hardware simulator
Author :
Cheng, Chung-Kuan ; Wei, Yen-Chuen ; Wurman, Zéev
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
Abstract :
The authors demonstrate the effectiveness of the ratio cut algorithm used in conjunction with a multistage heuristic in addressing very-large-scale partitioning problems. A very-large-scale system may contain several million gates. To achieve an optimal mapping of such a system onto a fixed hierarchy hardware accelerator presents a formidable challenge to even the fastest computing engines currently available. The authors describe the application of a divide-and-conquer heuristic coupled with the algorithm that solves the problem under a variety of constraints. The goal of this approach is to minimize the communication cost in the hierarchy. The authors describe experiments with designs containing up to two million gates, and demonstrate that the approach decreased communication costs by a factor of two or more, when compared with other approaches. This approach enables the hardware simulator to perform approximately three billion gate evaluations/s, or approximately 200 million event evaluations in an event-driven simulator, using a 6% activity rate
Keywords :
VLSI; circuit layout CAD; integrated logic circuits; logic CAD; activity rate; communication cost minimization; divide-and-conquer heuristic; event-driven simulator; fixed hierarchy hardware accelerator; logic designs mapping; multistage heuristic; optimal mapping; ratio cut algorithm; very large scale hardware simulator; very-large-scale partitioning problems; very-large-scale system; Computational modeling; Computer simulation; Costs; Discrete event simulation; Engines; Hardware; Large-scale systems; Logic design; Modems; Time division multiplexing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176803