DocumentCode
2834139
Title
A new placement algorithm minimizing path delays
Author
Hasegawa, Takashi
Author_Institution
Hitachi Ltd., Tokyo, Japan
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2052
Abstract
The author presents a new placement algorithm that minimizes path delays. The proposed algorithm first detects all paths and calculates path delays from the net list. It then improves the locations of flip-flops after random or initial placement. The locations of the terminals are then improved using the FDPR (force direct pairwise relaxation) method. Lastly, the locations of cells with fixed flip-flop locations are improved using the FDPR method again. Since this method controls the nets which constitute each path as a group, it can improve path delays better than methods which consider only the net length
Keywords
VLSI; circuit layout CAD; minimisation; FDPR; all paths detection; cells locations improvement; flip-flops locations improvement; force direct pairwise relaxation; minimizing path delays; net list; path delays calculation; placement algorithm; terminals locations improvement; Capacitance; Delay; Design optimization; Equations; Fabrication; Flip-flops; Integrated circuit interconnections; Laboratories; Routing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176807
Filename
176807
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