The Testware CAD

ATPG (Automatic Test Pattern Generation) for arbitrary digital circuit is not possible without previously verification feature been realized at first and without testability been estimated and changed to appropriate level as second. ATPG for arbitrary digital circuit is not possible without hazard free sequences generation at third. At forth ATPG is divided into two versions: for verification test pattern generation and for hardware test pattern generation. CAD combined all four listed features is denoted as the Testware CAD. Our Testware CAD provides Design for Test & Test for Design technology (in brief DFT & TFD). Data about such kind system are described here and more completely at site http://twcad.ifmo.ru.