Title :
Modeling on-chip variations in digital circuits using statistical timing analysis
Author :
Petrosyan, Gor ; Abovyan, Sargis ; Harutyunyan, Tigran
Author_Institution :
Synopsys Armenia CJSC, Yerevan, Armenia
Abstract :
The purpose of this paper is to model timing of digital circuits by determining dependencies between the logical depth of standard cells in digital circuit and variation margins applied during timing analysis. The simulation results for the cells used in clock tree are presented.
Keywords :
clocks; digital integrated circuits; integrated circuit modelling; timing; clock tree; digital circuits; logical depth; on-chip variations; standard cells; statistical timing analysis; variation margins; Analytical models; Delay; Digital circuits; Integrated circuit modeling; Inverters; Monte Carlo methods;
Conference_Titel :
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location :
St. Petersburg
Print_ISBN :
978-1-4244-9555-9
DOI :
10.1109/EWDTS.2010.5742038
