Title :
Area optimization for general floorplans: an analogy to resistive networks
Author :
The, Khe-Sing ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
The authors present an algorithm for general floorplans in which each module has an infinite set of possible dimensions. Given the topology of a floorplan and the possible dimensions of the modules, the floorplan area optimization problem is to determine the dimensions of all the modules in order to minimize the floorplan area. The optimization algorithm is based on an analogy between reducing floorplan area and solving resistive network equations. Experimental results show that the algorithm outperforms the one proposed by D.F. Wong and P. Sakhamuri (1989)
Keywords :
circuit layout CAD; monolithic integrated circuits; optimisation; floorplan area minimization; floorplan area optimization problem; optimization algorithm; resistive network analogy; Algorithm design and analysis; Circuit topology; Computer networks; Equations; Flexible printed circuits; Heuristic algorithms; Integrated circuit interconnections; Iterative algorithms; Network topology; Shape;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176808
