Fault modeling and testing generation for sample-and-hold circuits

The author presents the first comprehensive study of fault modeling of the class of sample-and-hold circuits frequently used in mixed analog/digital signal processors. The faults under study consist of catastrophic faults and out-of-specification faults. Even if the faults are restricted to the passive components and MOS switches (i.e. the operational amplifiers are assumed fault-free), the effects of these faults are quite complex, especially the out-of-specification faults. For example, an incorrect value of the resistor R_on of an MOS switch and an incorrect value of the capacitor in some cases have the same faulty manifestations at the output, and may be thought of as equivalent faults. The concept of fault equivalence is validated for analog circuits. The results show that various types of faults are distinguishable, thus reducing the size of the analog fault dictionary used in further diagnosis