DocumentCode
2834244
Title
Parallelizing of Boolean function system for device simulation
Author
Chemeris, Alexander ; Reznikova, Svetlana
Author_Institution
G.E.Pukhov Inst. for Modeling in Energy Eng., Kiev, Ukraine
fYear
2011
fDate
9-12 Sept. 2011
Firstpage
200
Lastpage
202
Abstract
The representation of digital circuits that are designed by Boolean functions is considered. The syntax of Boolean function we use is presented. This digital circuit representation in the form of data-flow graph is used as a basis for parallelizing of simulation process for multiprocessor computers.
Keywords
Boolean functions; data flow graphs; digital circuits; digital simulation; logic design; microprocessor chips; multiprocessing systems; Boolean function syntax; Boolean function system; data flow graph; device simulation; digital circuits representation; multiprocessor computer; simulation process; Boolean functions; Computers; Equations; Integrated circuit modeling; Mathematical model; Processor scheduling; Program processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2011 9th East-West
Conference_Location
Sevastopol
Print_ISBN
978-1-4577-1957-8
Type
conf
DOI
10.1109/EWDTS.2011.6116583
Filename
6116583
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