Title :
Analysis and optimization of BiCMOS gate circuits
Author :
Kuroda, Tadahiro ; Sakata, Yoshinori ; Matsuo, Kenji
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
An optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed whose parameters can be extracted with SPICE simulations. Therefore a device model can be precise, while keeping the optimization procedure simple and unchangeable in any device generation. With the proposed procedure, BiCMOS gate delays can be calculated quickly and optimized efficiently just by looking up design tables that are obtained easily and are applicable to any design with the same device technology. The sizing strategy of cascaded drivers is also studied. BiCMOS-BiCMOS cascaded buffers are optimized when the scale-up factor is e2.3, while BiCMOS-CMOS cascaded buffers become the fastest when the scale-up factor, e1.6 , is employed. The strategy was successfully applied to the design of high-speed BiCMOS static-RAM (SRAM) macros for standard cell libraries
Keywords :
BIMOS integrated circuits; SRAM chips; buffer circuits; cascade networks; delays; integrated logic circuits; logic design; optimisation; BiCMOS SRAM macros; BiCMOS gate circuits; BiCMOS-BiCMOS cascaded buffers; BiCMOS-CMOS cascaded buffers; SPICE simulations; cascaded drivers; design tables; gate delay model; optimization strategy; scale-up factor; sizing strategy; standard cell libraries; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Circuit simulation; Delay; Design optimization; MOSFETs; Random access memory; SPICE; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176816
