Test minimization technique for multiple stuck-at faults of combinational circuit

In this paper the problem of test minimization technique for multiple stuck-at faults of combinational circuit derived from irredundant system sums-of-product (ISSOP) is considered. For minimizing of test length for considered circuit approach described in work [6] is used. The main steps of the minimization approach is a finding the root of the logical equation with a smaller rank and the extracting all the maximum compatible subsets.