DocumentCode
2834317
Title
An approach for PSL assertion coverage analysis with high-level decision diagrams
Author
Jenihhin, Maksim ; Raik, Jaan ; Ubar, Raimund ; Shchenova, Tatjana
Author_Institution
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
fYear
2010
fDate
17-20 Sept. 2010
Firstpage
13
Lastpage
16
Abstract
The paper presents an approach for assertion coverage analysis targeted at quality assessment of simulation-based verification stimuli and design error debug. The approach considers high-level decision diagrams based design verification flow and relies on temporally extended high-level decision diagrams for PSL assertion representation. The discussed case study illustrates the advantages of the proposed idea.
Keywords
decision diagrams; formal verification; specification languages; PSL assertion coverage analysis; Property Specification Language; assertion representation; design error debug; design verification flow; high-level decision diagrams; quality assessment; simulation-based verification stimuli; Analytical models; Boolean functions; Computational modeling; Hardware design languages; IEEE standards; Integrated circuit modeling; Measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location
St. Petersburg
Print_ISBN
978-1-4244-9555-9
Type
conf
DOI
10.1109/EWDTS.2010.5742048
Filename
5742048
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