Thermal aware test scheduling for stacked multi-chip-modules

In an attempt to increase the area utilization of multi-chip packages, manufacturers have started looking at 3D packaging. The 3D structures have either dies or chips stacked one above the other. These 3D structures have low thermal capabilities, and hence the thermal issues get aggravated during testing. In this paper, thermal aware test scheduling techniques for stacked structures is proposed. Care is taken to schedule the stacked partitions appropriately to prevent local heating and achieve uniform vertical temperature spread. Concurrent testing of dies is considered for reduced test time and existing test architecture is employed. The widely used global peak power model gives a pessimistic estimate of the power profile. A new partition scheme is proposed for the power profile based on power variations and true power. This scheme of power profile partitioning which is a trade-off between a cycle accurate model and global peak model offers both flexibility during scheduling and also reduces total false power. The power profile partitions are scheduled through algorithms based on heuristics. System model of the 3D stack is obtained from the linear RC-models after considering the various factors that affect the heat flow and die temperatures. Simulation results show that the proposed technique achieves uniform temperature spread across the 3D structure.