The use of stabilized CMOS delay lines in the digitization of short time intervals

The authors present the basic advantages and limitations of using integrated CMOS delay lines for the digitization of short time intervals. A 6-7-bit accuracy and a single-shot resolution of 0.5-10 ns are demonstrated using fully integrated, tapped and voltage controlled CMOS delay lines as a time base for the measurement. The delay lines considered are found to be most suitable for applications where better than 8-bit accuracy and 0.5-10-ns single-shot resolution is required. The accuracy is limited by the poor matching of minimum-sized structures, which causes more than ±0.5 lsb nonlinearity when the length of the delay line exceeds about 100 elements (7 bits)