DocumentCode
283451
Title
A solution to high performance acceleration of digital system design
Author
Carlstedt-Duke, T.
Author_Institution
Daisy Systems UK Ltd., Basingstoke, UK
fYear
1988
fDate
32391
Firstpage
42461
Lastpage
42469
Abstract
Describes a hardware simulation accelerator that has been designed to handle components of extreme complexity (such as microprocessors) as well as incorporating advanced architectures to provide maximum simulation speed for low level primitives (e.g. ASICS). The issue of mixed-level component modelling for system design is considered first, and then the architecture of the accelerator, known as the GigaLOGICIAN is examined in conjunction with the design objectives
Keywords
circuit CAD; digital systems; logic CAD; ASICS; GigaLOGICIAN; advanced architectures; digital system design; hardware simulation accelerator; high performance acceleration; low level primitives; microprocessors; mixed-level component modelling;
fLanguage
English
Publisher
iet
Conference_Titel
Hardware Accelerators for VLSI CAD - A Tutorial, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
209442
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