Title :
IEEE 1500 compliant test wrapper generation tool for VHDL models
Author :
MIkhtonyuk, Sergey ; Davydov, Maksim ; Hwang, Roman ; Shcherbin, Dmitry
Author_Institution :
Design Autom. Dept., Kharkiv Nat. Univ. of Radio Electron., Kharkiv, Ukraine
Abstract :
This paper presents a method of automated test wrapper generation implemented in new CAD tool “Boundary Scan Generator”. The tool can be used for generating IEEE 1500 compliant test wrappers and corresponding CTL-programs from VHDL descriptions of integrated circuits. The tool is designed as cross-platform and extendable development environment, based on open interfaces and modular architecture.
Keywords :
automatic test pattern generation; boundary scan testing; hardware description languages; integrated circuit testing; technology CAD (electronics); CAD tool; CTL-program; IEEE 1500 compliant test wrapper generation tool; VHDL model; automated test wrapper generation; boundary scan generator; cross-platform development environment; extendable development environment; integrated circuit; modular architecture; open interface; Design automation; Generators; Integrated circuit modeling; Libraries; Semantics; Solid modeling; Syntactics;
Conference_Titel :
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location :
St. Petersburg
Print_ISBN :
978-1-4244-9555-9
DOI :
10.1109/EWDTS.2010.5742069
