Assertion based verification in TLM

Design verification is an important matter in digital design process. There are many different ways to verify designs. One of these methods is based on assertions. In this method, the properties of the design are defined in terms of assertions which are fired in case of any contradiction to those properties. On the other hand, the emergence of higher abstraction levels to describe the digital circuits necessitates new and novel verification methods for the new abstraction levels. In this paper, we propose a method of assertion based verification for Transaction Level Modeling (TLM) by completing SystemC assertions and manipulating the TLM-1.0 library. This general purpose set of assertions can be used to efficiently debug and verify circuits described in TLM.