Architecture design and technical methodology for bus testing

In this paper we present an architecture and corresponding algorithm for bus testing in the System on Chip (SoC) design. In our test methodology we used hierarchical functional testing to test all available components in a bus except cores of the SoC as fast as possible. According to our proposed method, first small components and wires are tested and then, higher level operations of the bus (like burst transfers) will be tested. For each step of bus testing, an architecture is proposed. We show the efficiency of our proposed method using a real SoC as experimental result.