Generating test patterns for sequential circuits using random patterns by PLI functions

In this paper, a method for generating test patterns for sequential circuits while designing the circuits is presented. By the aim of this approach, hardware designers can obtain test patterns for their sequential designs while designing the circuit by an HDL, without any need of software languages and reformatting the design for evaluation and application of test generation methods. PLI (Procedural Language Interface) functions are used for fault injection, fault collapsing, and fault simulation. The main idea of test generation method is selecting appropriate sequence of patterns among random patterns.