Early detection of potentially non-synchronized CDC paths using structural analysis technique

The number of independent clock domains found on the typical today´s device is continuously growing. According to the latest industry research, the average number of clock domains on a single device is >;15-20 and it becomes higher and higher from day to day. The CDC-related design flaws are also growing exponentially, appearing to be very dangerous as the roots of intermittent chip failures (can be found only in the silicon). Static CDC verification is considered as one of the first de-facto steps in today´s SoC design methodology; only static techniques can work as soon as the RTL starts taking shape. This paper discusses early detection of potentially missing synchronizers on clock domain crossing paths, using structural static analysis.