DocumentCode
2834886
Title
Analysis and simulations of interconnects in high-speed integrated circuits
Author
Chowdhury, S. ; Daisun, Z. ; Bai, E.W. ; Lonngren, K.E.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., IA, USA
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2379
Abstract
The authors deal with transmission line analysis of high speed interconnects connected in a general graph topology. The method proposed allows monitoring voltage/current at discrete time intervals at user-designated points on an interconnect system of any topology. The discrete-time signals on transmission lines are related by simultaneous equations in time and space (points on a net). However, delay property of the transmission lines can be used to obtain the signal value at a node at a given time from the signal values at adjacent nodes at some previous times. Computing time is linear with respect to the number of nodes and also linear with respect to the number of time points for which simulation is desired. Accuracy and storage requirements of the proposed method, in general, depends on the time step to be used. Included are preliminary results on stability analysis which may lead to design rules for reliable design of interconnect structures
Keywords
integrated logic circuits; metallisation; transmission line theory; delay property; design rules; discrete-time signals; graph topology; high-speed integrated circuits; interconnects; reliable design; stability analysis; storage requirements; time step; transmission line analysis; Analytical models; Computational modeling; Delay effects; Equations; High speed integrated circuits; Monitoring; Stability analysis; Topology; Transmission lines; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176857
Filename
176857
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