A mixed-mode simulator for digital/analog VLSI circuits using an efficient timing simulation approach

The authors describe a mixed-mode timing simulator which combines logic simulation with assignable delay, macromodel-based timing simulation and circuit simulation, all of which utilize a common database. The mode in which a given part of the circuit is to be simulated is specified as part of the input. However, in certain cases, such as the occurrence of glitches or nonmonotonical changes in subcircuit outputs, the simulator automatically chooses the most accurate simulation level appropriate for that particular case. The implementation of the algorithms in the simulator is briefly described and sample simulation examples are presented