Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD

A method of combined state assignment is proposed which targets on a decrease in the hardware amount (the number of PAL macrocells) in combinational part of Moore finite-state-machine (FSM). Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount. It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of refined state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. Example of proposed method application is given.